• 2Gbit/sec Maximum Data Rate
• 1GHz Analog Bandwidth for All Parametric Measurements
• Pattern Generator with 1psec Resolution of Bit Precompensation*
• PRML Chip Integration to 2Gbit/sec
• Servo Writing and Processing

Pattern Generator

• Minimum bit cell: 500psec
• Absolute position accuracy for any transition: 5psec (typ) 10psec (max)
• Precompensation resolution for any transition: 1psec
• Jitter at 2Gbit/sec
  • Repetitive Pattern: 2psec RMS (typcal).
  • Pattern Dependent Jitter, 5psec peak-to-peak (typical).
• Frequency resolution: better then 1Hz
• Frequency stability: ±2.5ppm up to 75°C, ±1ppm/year
• Random pattern maximum length: up to 2Mbit

PRML Chip Integration

• Data Rate: up to 2Gbit/sec (limited by available commercial PRML chips).
• PRML chips: Cirrus Logic, Data Path, GEC Plessey, IBM, Lucent
  Technology, Marvell, NEC, SSI, and new PRML chips integrated on request.
• Channel Optimization
• Wide range of PRML Tests

Analog Channel

• Bandwidth: more than 1GHz at - 3dB
• Flatness: ± 0.2dB up to 1GHz
• Group delay: ±100psec up to 1GHz
• Non-linear distortion: better than 1%
  (entire bandwidth, nominal level)
• Minimum pulse width (PW)
  to be measured: 330psec
• Parametric measurement accuracy
  (entire bandwidth):
  
  • TAA: ±0.5dB***
  • Pulse width: 3% or 20psec (whichever is greater)***
  • SNR: ±0.5dB
  • Modulation: ± 2%***
  • Crest factor: ± 2%
  • Overwrite: ± 0.2dB

Physical Specifications

• Size: 22.1" x 17.6" x 10.8"
• Weight: 46 lbs
• Power: 100-240 VAC (± 10%, 50/60 Hz, 3A)

* Patent Pending

** Specifications are subject to change without notice.

*** Measurement conditions: sinewave signal without noise.