WITE Revision 1.221 Release Notes

New Software Features:

• New revisions of SSI4915 PRML chip - SSI4915C1, SSI4915C2, SSI4915C3, SSI4915A are now supported.

• Automatic Equalization procedure is implemented

• New Spectrum Analyzer Board (replacement of Overwrite Filter Matrix) is supported by WITE.

1. Spectrum Analyzer Board is made compatible with standard Overwrite filter matrix software. Arbitrary values of overwrite filters from 0.5 MHz up to 150 MHz can be typed into the Filter Configuration window and overwrite measurements can be performed at arbitrary specified frequencies

2. New Spectrum Analyzer Test has been added. The test allows to scan read-back signal spectrum

• New test for MR Transfer curve measurement is implemented (2 Gsamples/s ADC option required)

• New NLTS tests have been included into release:

1. The harmonic elimination test is modified to support patterns of different periods (30 and 20). This modification provides improved NLTS estimate.

2. New harmonic elimination test supports new patterns having one, two dibits, tribits and 4 transitions is implemented. New software also provides calculation of density units in Mflux or Kfci.

3. Partial Erasure measurement using method of third harmonic ( Spectrum analyzer board required)

4. Linearized measurements of NLTS and Partial Erasure for MR heads are now possible using linearized read-back signals ( 2 Gsamples/s ADC required)

• A new command 'CommitResult' has been added for backward communication between an external module and WITE. This can be used along with 'WITEExecute' command to ensure the presence of the output results in the Result Database right after the submitted test finishes.

• Normalization for the 'Resolution' in the Parametric Test has been made available through the multiplicative correction. It was done at a customer request.

Bugs Fixed:

• Previous version of the Comparator Test was slow compared to previous revisions of WITE. Performance of the test has been reinstated by optimizing WRITE/READ/PatternSelect sequence where each of them might have been taken substantial time.

• SSI48xx series of PRML chips produced higher Error Rate because of misalignment of RWA clock generator with the PRML chip clock generator resulting in incorrect ReadGate signal timing. SSI48xx clock generator now always provides correct ReadGate timing. Incorrect limits of the maximal data rate frequency have been fixed.

• Chip Parameter Optimization Test now supports optional rewriting PRML pattern before setting each value to a register. The option is called "Write Permanently".

• Adding patterns for new NLTS tests (mainly using a programmable overwrite filter) to existing file PRML.PDL leads to memory overflow because of pattern memory of WITE is limited. To avoid the overflow file PRML.PDL has been broken down into two files: PRML.PDL and NLTS.PDL.

• Under certain circumstances 'Insert new test' in Production caused 'Divide by Zero' error message and the system hung up.

• Print button was missing in internal Piezo Range test plot in WDCP module.

• Sometimes a combination of DSP Piezo Controller rev. F or highier and S312MP or S1701MP spinstand produced the error message "Invalid response on Piezo Voltage request"