with the ADP7104 16/32 Gsa/s 10-bit digitizers
- Full band external frequency and phase response FPGA-based S-parameter de-embedding
- Real-Time external frequency and phase response de-embedding with Real-Time DDC with up-to 2.5 GHz user band.
- Up-to 640 tap FIR equalizing filter for full band
- 160 tap FIR equalizing filter for Real-Time DDC
It is a known fact that time‐interleaving of Analog‐to‐Digital Converters (ADC) is used to increase sampling rate of modern high‐performance digitizers. For example, the 10‐bit digitizers from Guzik Technical Enterprises (GTE) feature Keysight Technologies ADC Integrated Circuit (IC), where 160 individual ADC are interleaved to achieve sampling at up‐to 64 Gsa/s (160 “slices” sampling at 400 Msa/s) forming two analog channels at 32 Gsa/s each. Time‐interleaving that many ADCs makes it challenging to achieve high Spurious‐Free Dynamic Range (SFDR). Patented digital equalization technology (US Patent 7,408,495) is used to reduce mismatch between slices, nonflatness of Frequency Response (FR) and Group Delay (GD) (US Patent 9,933,467) of the Digitizer, to create a calibrated baseband receiver channel in DC ‐10 GHz band with input signal range from ‐32 dBm to +22 dBm.
The same digital equalizer, which is used to equalize the frequency response amplitude non-flatness and group delay of the digitizer internal signal path through front-end and the ADC is used to de-embed down-converters, cables, couplers, attenuators and other components external to the digitizer. Note the de-embedding functionality requires ADC_BB license.
S-parameter files are typically used with oscilloscopes and digitizers for de-embedding and embedding. S-parameters can be measured, directly, with vector Network Analyzers (VNAs) and Time Domain Reflectometers (TDRs). The detailed use of VNAs and TDRs to measure the S-parameter file for an external circuit element is beyond the scope of this document.
Guzik External Frequency Response Manager software allows to load Touchstone S-parameter files for de-embedding purposes. 2-port touchstone files are identified by the file extensions .s2p. The size of S-parameter files depends directly on the frequency resolution and maximum frequency of the data. When loading the S-parameter file into the External Frequency Response Manager the software computes the appropriate FIR filter coefficients for each digitizer input channel based on the provided frequency resolution of the S-parameter file. Hardware FIR tap use is maximized to achieve the best de-embedding quality possible when embedding the external frequency amplitude response and phase error to the digitizer internal frequency response and phase response. Below is an example of de-embedding a .s2p S-parameter file (DC – 10 GHz with 33.3 MHz steps):
Corrected digital edge trigger functionality
Since the acquired waveform gets corrected to reflect the original signal before the signal path, the digital trigger functionality also takes advantage of this. It allows to use and display the exact trigger location on the signal before the signal path and digitization.
Vector Signal Analysis
For demonstration purposes only as an example we will use the Keysight M8195A Arbitrary Waveform Generator to create a waveform and the Guzik ADP7104 digitizer and Keysight VSA 89600 Software to Analyse the digitized modulated waveform.
The signal path consists of 2x 6dB attenuators and a SMA-SMA coax cable.
The 16-QAM signal with 2.5 GHz symbol rate centered at 8 GHz shows an EVM of ~4.3% (-27.3 dB):
Once we have figured out the end-to-end frequency response by running adaptive equalization we can apply the resulting adaptive equalizer response using the Guzik External Frequency Response Manager and compensate for both external amplitude frequency response and group delay/phase error in the digitizer hardware:
Now we can observe that the linear amplitude and phase errors of the signal path have been de-embedded and the resulting EVM is ~2.6% (-31.7 dB):
Note that analysis Measurement Loop time was not affected by the extra de-embedding operation.
The equalization is done in hardware inside the FPGA‐based Digital Processor of the Guzik ADP7000 Series Digitizers in real‐time for signals with bandwidth up to 2.5 GHz using the patented Digital Downconverter (DDC) (US Patent 9,634,679). Real-Time DDC Specification (requires ADC_ADDCRT1 license)
To find out how the real-time de-embedding was used to create a mmWave 5G 28 GHz wideband receiver with known amplitude frequency and phase response navigate to Technical Library.
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